后摩尔时代的碳基电子技术: 进展、应用与挑战

图 11  碳纳米管晶体管的scaling down极限[19]　(a), (c) P型和N型碳纳米管晶体管的透射电子显微镜(TEM)截面图, 其中沟道和栅极长度分别为20 nm和10 nm; (b), (d) 碳纳米管和硅CMOS FET的门延迟和能量延迟积(EDP)随栅长缩减的变化趋势比较, 蓝色实线表示P型硅FET的实验数据拟合, 而绿色实线表示N型硅FET, 蓝色星和绿色星分别代表P型和N型碳纳米管晶体管; (e), (f) 5 nm栅长碳纳米管晶体管的扫描电子显微镜(SEM)俯视图及其转移特性曲线

Fig. 11.  Scaling down limit of carbon nanotube transistors[19]. (a), (c) Cross-sectional TEM micrographs of P-type and N-type carbon nanotube FETs, where the channel and gate lengths are respectively 20 nm and 10 nm. (b), (d) comparisons of scaling trends of gate delay and EDP between CNT and Si CMOS FETs. Blue solid line indicates the experiment data fitting for the P-type Si-MOSFETs, whereas green solid line indicates the N-type Si-MOSFETs, the blue and green stars respectively represent the P-type and N-type CNTFETs. (e), (f) SEM top view and transfer characteristic curves of a 5 nm gate length carbon nanotube transistor.